年度101
論文名稱(篇名)Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs
期刊名ACM Trans. on Design Automation of Electronic Systems
出版日期2012-06
期數3
總頁數22
作者中文名蔡加春
作者英文名Chia-Chun Tsai
使用語言外文